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1993-11-09
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846b
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24 lines
!Documentation
(c) Copyright 1993 Genashor Corp. All rights reserved.
This circuit demonstrates a number of features of the Simic
Fault simulator. Including the resolution of potential detections
and the removal of undetectable faults.
The circuit is a Johnson counter (shift register with complementary
feedback) containing positive edge triggered D flip-flops with
active low asynchronous SET and RESET inputs. These inputs,
tied to the normally high signal, Inactive, are disabled, and
topologically invisible elements are introduced.
!Logical
!Format Part= Type= I= O=
Type=Fcount I=Clear,Clock O=Q3
Back Nor Clear,Q3
F1 Dpcf Inactive,Inactive,Clock,Back Q1
F2 Dpcf Inactive,Inactive,Clock,Q1 Q2
F3 Dpcf Inactive,Inactive,Clock,Q2 Q3
Q1bar Inv Q1
Oops Nand Q1bar,Back
Inactive Inv ZERO